Digital Processing Phase-locked Loop for Network Synchronization

He Yan

doi:10.13756/j.gtxyj.1989.02.004

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Digital Processing Phase-locked Loop for Network Synchronization

- Digital Processing Phase-locked Loop for Network Synchronization
- Study on Optical communication Issue 2, Pages: 28-34(1989)
- 作者机构：
  
  邮电部激光通信研究所
- 作者简介：
- 基金信息：
- DOI：10.13756/j.gtxyj.1989.02.004
  CLC：
- Published：1989，
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[1]何岩.用于网同步的数字处理智能锁相环[J].光通信研究,1989(02):28-34.

He Yan. Digital Processing Phase-locked Loop for Network Synchronization. [J]. (2):28-34(1989)
[1]何岩.用于网同步的数字处理智能锁相环[J].光通信研究,1989(02):28-34. DOI： 10.13756/j.gtxyj.1989.02.004.

He Yan. Digital Processing Phase-locked Loop for Network Synchronization. [J]. (2):28-34(1989) DOI： 10.13756/j.gtxyj.1989.02.004.

摘要

把大规模集成电路和计算机结合

构成数字处理智能锁相环（DP-PLL）。DP-PLL依靠存贮程序控制获得较好的同步性能

可以抑制很低频率的相位抖动及具有一定抗输入信号扰动的能力

是实现网同步的理想部件。本文主要论述DP-PLL系统的结构、设计方法和实验结果。

Abstract

By combining LSI with computers

an intelligent phase-locked loop using digital processing （DP-PLL） can be created. It features a excellent performance of synchronization by a stored program control

and it is an ideal component for network synchronization

because it is able to suppress the ex（?）remely low frequency jittering and can tolerate disturbances of input signal. This paper mainly describes the structure and the design method of the DPPLL. The results of the experiment and the test of the DP-PPL are also presented.

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