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武汉邮电科学研究院,湖北,武汉,430074
Published:1999,
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[1]江榕,田立人.SDH解同步电路设计[J].光通信研究,1999(04):1-3+7.
JIANG Rong, \ TIAN Li ren. Design of Desynchronous Circuit in SDH System. [J]. (4):1-3(1999)
[1]江榕,田立人.SDH解同步电路设计[J].光通信研究,1999(04):1-3+7. DOI: 10.13756/j.gtxyj.1999.04.001.
JIANG Rong, \ TIAN Li ren. Design of Desynchronous Circuit in SDH System. [J]. (4):1-3(1999) DOI: 10.13756/j.gtxyj.1999.04.001.
在SDH 同步系统中,解同步电路直接关系到输出抖动的指标,设计的关键是比特泄漏和锁相环电路。本文使用自适应比特泄漏法,给出了一个比特泄漏和锁相环电路设计实例,并给出了测试结果
In SDH system desynchronizer
the bit leaking and PLL circuit is the key technical problem in the design. This paper describes a example of the desynchronous circuit which based on adaptive bit leaking
and the jitter measurement result is given.
比特泄漏锁相环抖动
bit leaking\ PLL\ jitter
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