The Design of SDH E1  VC4 Integrated System

JIN De  peng; \ QIN Xiao  yi; \ SHA Yan  ping; \ ZENG Lie  guang

doi:10.13756/j.gtxyj.1999.04.004

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The Design of SDH E1 VC4 Integrated System

- The Design of SDH E1 VC4 Integrated System
- Study on Optical communication Issue 4, Pages: 13-16(1999)
- 作者机构：
  
  清华大学电子工程系!北京100084
- 作者简介：
- 基金信息：
- DOI：10.13756/j.gtxyj.1999.04.004
  CLC： TN914.332
- Published：1999，
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[1]金德鹏,秦晓懿,沙燕萍,曾烈光.E1-VC4的SDH集成化系统设计[J].光通信研究,1999(04):13-16.

JIN De peng, \ QIN Xiao yi, \ SHA Yan ping, et al. The Design of SDH E1 VC4 Integrated System. [J]. (4):13-16(1999)
[1]金德鹏,秦晓懿,沙燕萍,曾烈光.E1-VC4的SDH集成化系统设计[J].光通信研究,1999(04):13-16. DOI： 10.13756/j.gtxyj.1999.04.004.

JIN De peng, \ QIN Xiao yi, \ SHA Yan ping, et al. The Design of SDH E1 VC4 Integrated System. [J]. (4):13-16(1999) DOI： 10.13756/j.gtxyj.1999.04.004.

摘要

介绍一种ＳＤＨ系统专用集成电路的设计，它可以从ＶＣ４信号中任意上下分插出多达２１个Ｅ１信号，包括Ｅ１的线路编解码及数字解同步器、码速调整及去调整、ＶＣ１２开销的终结及生成、ＴＵ１２的指针调整及解释、ＶＣ４的合成及分解。电路设计既充分考虑ＩＴＵ－Ｔ的标准，又结合实际系统设计，克服了以前电路的缺点，具有规模大、功能完善、性能优越的特点

Abstract

This paper introduces the design of a Synchronous Digital Hierarchy（SDH） Application Special Integrated Circuit（ASIC）. The chip can demultiplex and muiltiplex up to 21 E1 signals form and to VC4 frame including codec of E1 line signal

digital desynchronizer

bit rate justification

TU12 pointer interpretation and generation

VC12 overhead termination and generation. The design of the chip not only accords with the ITU T recommendiations but also considers the system application. It has the characters of large scale

comprehensive functions and perfect performances.

关键词

同步数字系列专用集成电路上下分插复用终端复用自愈环

Keywords

SDH\ ASIC\ add and drop multiplexer\ terminal multiplexer\ self healing ring

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Wuhan Research Institute of Posts and Telecommunications

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