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The design of DPLL for clock recovery and digital jitter attenuation
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    • The design of DPLL for clock recovery and digital jitter attenuation

    • Study on Optical communication   Issue 5, Pages: 46-49(2003)

    • DOI：10.13756/j.gtxyj.2003.05.013    

      CLC： TN915

    • Published：2003，

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  • The design of DPLL for clock recovery and digital jitter attenuation. [J]. (5):46-49(2003) DOI： 10.13756/j.gtxyj.2003.05.013.

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State Key Laboratory of Information Photonics and Optical Communications, Beijing University of Posts and Telecommunications
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  北京格林威尔科技发展有限公司 北京100085  
  北京100876  
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