The function verification of integrated circuits has become the bottleneck of the design cycle because of the increasing scale and the complexity of chips. In order to verify the design of ASIC chip in the field of SDH

this paper presents a primary verification platform

which includes various layers for specifying test benches and a library of standard data

as well as some C programs for comparing simulation dada with expected data. The platform has been use for verifying the design of 40 Gbit/s switch chip with satisfactory results.