A high-speed and low-jitter CDR circuit for fiber-optic communications

CHEN Jiesheng; LAI Xinquan; GUO Xiaofeng

doi:10.13756/j.gtxyj.2006.03.005

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A high-speed and low-jitter CDR circuit for fiber-optic communications

- A high-speed and low-jitter CDR circuit for fiber-optic communications
- Study on Optical communication Issue 3, Pages: 15-18(2006)
- 作者机构：
  
  1. 西安电子科技大学电路CAD研究所
  2. 西安电子科技大学电路CAD研究所陕西西安710071
- 作者简介：
- 基金信息：
- DOI：10.13756/j.gtxyj.2006.03.005
  CLC： TN929.11
- Published：2006，
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[1]陈杰生,来新泉,郭晓峰.光纤通信用低相位抖动时钟数据恢复电路[J].光通信研究,2006(03):15-18+57.

CHEN Jiesheng, LAI Xinquan, GUO Xiaofeng. A high-speed and low-jitter CDR circuit for fiber-optic communications. [J]. (3):15-18(2006)
[1]陈杰生,来新泉,郭晓峰.光纤通信用低相位抖动时钟数据恢复电路[J].光通信研究,2006(03):15-18+57. DOI： 10.13756/j.gtxyj.2006.03.005.

CHEN Jiesheng, LAI Xinquan, GUO Xiaofeng. A high-speed and low-jitter CDR circuit for fiber-optic communications. [J]. (3):15-18(2006) DOI： 10.13756/j.gtxyj.2006.03.005.

摘要

文章阐述了一种适用于光纤通信的锁相环（PLL）时钟数据恢复电路结构。该结构采用负阻放大形式构成二阶有源低通滤波器

并用PECL环形延时单元构成压控振荡器（VCO）

工作在80

00 MHz的频率范围内

峰-峰相位抖动

20 ps

锁定时间

600 ns。实际电路在计算机上仿真成功

版图后仿真验证也已通过

并进行了投片。

Abstract

A low-jitter PLL CDR circuit for fiber-optic communications is introduced

which adopts a second-order active LP filter using negative-impedance amplification and forms a VCO with PECL ring time-delay elements

operating within the range of 80～500 MHz with the peak-peak jitter <20 ps and the phase-lock time <600 ns.Both pre-and post-layout simulations of the actual circuit prove to be successful.

关键词

时钟数据恢复低通滤波锁相环非归零

Keywords

CDRlow-pass filterPLLNZR

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