Design of an application-specific chip for circuit emulation

Zhang Pengcheng; Su Li; Jin Depeng; Zeng Lieguang

doi:10.13756/j.gtxyj.2006.05.014

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Design of an application-specific chip for circuit emulation

- Design of an application-specific chip for circuit emulation
- Study on Optical communication Issue 5, Pages: 41-44(2006)
- 作者机构：
  
  1. 清华大学电子工程系
  2. 清华大学电子工程系北京100084
- 作者简介：
- 基金信息：
- DOI：10.13756/j.gtxyj.2006.05.014
  CLC： TN70;TN402
- Published：2006，
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[1]张鹏程,苏厉,金德鹏,曾烈光.电路仿真专用芯片设计[J].光通信研究,2006(05):41-44.

Zhang Pengcheng, Su Li, Jin Depeng, et al. Design of an application-specific chip for circuit emulation. [J]. (5):41-44(2006)
[1]张鹏程,苏厉,金德鹏,曾烈光.电路仿真专用芯片设计[J].光通信研究,2006(05):41-44. DOI： 10.13756/j.gtxyj.2006.05.014.

Zhang Pengcheng, Su Li, Jin Depeng, et al. Design of an application-specific chip for circuit emulation. [J]. (5):41-44(2006) DOI： 10.13756/j.gtxyj.2006.05.014.

摘要

电路仿真对于电信网向分组交换网的平稳过渡有着重要意义。文章根据相关标准提出并实现了一种电路仿真专用芯片的设计方案

并对其中主要功能模块和关键算法作出了详细说明

包括一种全数字的自适应时钟恢复方法、动态深度缓冲算法等。目前该设计已经通过了验证和在实际网络环境中的测试。

Abstract

Circuit emulation provides a seamless migration approach to backbone PSNs without interruption of legacy services.In this paper

the design of a specific chip for circuit emulation based on IP is put forward and realized and the main functional modules and the key algorithms including an all-digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail.The design has been verified and tested in actual networks.

关键词

电路仿真时钟恢复动态深度缓冲

Keywords

circuit emulationclock recoverydynamic depth buffering

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