Analysis and design of all digital phase-locked loops in SEC

Zhang Jiyong; Wang Aiguo

doi:10.13756/j.gtxyj.2006.06.008

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Analysis and design of all digital phase-locked loops in SEC

- Analysis and design of all digital phase-locked loops in SEC
- Study on Optical communication Issue 6, Pages: 22-23(2006)
- 作者机构：
  
  1. 武汉邮电科学研究院
  2. 烽火通信科技股份有限公司
- 作者简介：
- 基金信息：
- DOI：10.13756/j.gtxyj.2006.06.008
  CLC： TN79;TN911.8
- Published：2006，
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[1]张继勇,王爱国.SEC中的全数字锁相环的分析及设计[J].光通信研究,2006(06):22-23+41.

Zhang Jiyong, Wang Aiguo. Analysis and design of all digital phase-locked loops in SEC. [J]. (6):22-23(2006)
[1]张继勇,王爱国.SEC中的全数字锁相环的分析及设计[J].光通信研究,2006(06):22-23+41. DOI： 10.13756/j.gtxyj.2006.06.008.

Zhang Jiyong, Wang Aiguo. Analysis and design of all digital phase-locked loops in SEC. [J]. (6):22-23(2006) DOI： 10.13756/j.gtxyj.2006.06.008.

摘要

文章首先介绍了全数字锁相环（ADPLL）的基本结构和工作原理

并进行了数学建模

计算了其主要的参数指标;然后

针对SDH设备时钟（SEC）设计了一种切实可行的低抖动ADPLL的电路结构

并对其各个组成部分进行了具体的电路分析和设计

通过微机适当配置

可以使该设计的结果得到优化;最后

通过现场可编程门阵列（FPGA）验证

给出了测试结果。

Abstract

In this paper

the basic structure and operating principle of ADPLL（All Digital Phase-Locked Loop） are first introduced

which is followed by the analyses of its mathematic model and the calculation of its main parameters.Then

a feasible low-jitter ADPLL circuit structure for SEC（SDH equipment clock）is designed and specific circuit analysis of and designs for each part of ADPLL made

which is optimized by appropriate CPU configurations.Finally

this circuit is verified by FPGA and the test result given.

关键词

全数字锁相环数控振荡器分频器抖动

Keywords

ADPLLDigital-Controlled Oscillator（DCO）dividerjitter

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Shanghai Research Institute,China Telecom Co.,Ltd.

SKL of OCTN,Wuhan Research Institute of Post and Telecommunications

College of Electromechanical Engineering and Automation,National University of Defense Technology

国防科学技术大学机电工程与自动化学院湖南长沙410073

Wuhan Research Institute of Posts and Telecommunications

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