Design and implementation of EPON analyzer hardware platform

Fu Yunsheng~1; Chen Xue~1; Hu Jun~1; Wang Chenling~1; Liu Dong~2

doi:10.13756/j.gtxyj.2007.01.012

您当前的位置：

首页 >

文章列表页 >

Design and implementation of EPON analyzer hardware platform

- Design and implementation of EPON analyzer hardware platform
- Study on Optical communication Issue 1, Pages: 37-40(2007)
- 作者机构：
  
  1. 北京邮电大学
  2. 北京格林威尔科技发展有限公司
- 作者简介：
- 基金信息：
- DOI：10.13756/j.gtxyj.2007.01.012
  CLC： TN929.1
- Published：2007，
扫描看全文
[1]符运生,陈雪,胡骏,王晨凌,刘冬.EPON测试仪硬件平台的设计与实现[J].光通信研究,2007(01):37-40.

Fu Yunsheng~1, Chen Xue~1, Hu Jun~1, et al. Design and implementation of EPON analyzer hardware platform. [J]. (1):37-40(2007)
[1]符运生,陈雪,胡骏,王晨凌,刘冬.EPON测试仪硬件平台的设计与实现[J].光通信研究,2007(01):37-40. DOI： 10.13756/j.gtxyj.2007.01.012.

Fu Yunsheng~1, Chen Xue~1, Hu Jun~1, et al. Design and implementation of EPON analyzer hardware platform. [J]. (1):37-40(2007) DOI： 10.13756/j.gtxyj.2007.01.012.

摘要

随着基于以太网的无源光网络（EPON）商用规模的逐步扩大

不同厂商设备间的互通测试以及EPON系统的工程验收测试和运行维护变得日益迫切

为此我们设计开发了EPON测试仪。文章分析了EPON测试仪的功能需求

简述了EPON测试仪的总体框架

着重阐述了EPON测试仪硬件平台的设计及其核心功能的现场可编程门阵列（FPGA）的实现。

Abstract

With the growing commercial applications of Ethernet-based EPON and the daily increasing urgency for the interworking tests on equipment from different manufacturers and the EPON system project acceptance test and OAM

we have developed an EPON analyzer.In this paper

its functional requirements are analyzed and its general architecture briefly described

with the emphasis on the design of its hardware platform and the FPGA-based implementation of its core functions.

关键词

基于以太网的无源光网络协议分析互通测试现场可编程门阵列

Keywords

EPONprotocol analyzinginteroperation testFPGA

references

更多指标>

Views

160

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

The 2.5 Gbit/s Optical System Used in Illumination Guidance System based on Serial Parallel Transceiver

Real-time Implementation of Chaos Synchronization Using Neural Network based on FPGA

Real-Time and Parallel Post-Processing for High-Speed Quantum Random Number Generation

Implementation of Photoelectric Hybrid Interconnect Prototype System for Reconfigurable Video Array Processor

Design of Single-Chip Optical Network Unit based on High Speed Serial Transceiver

Related Author

No data

Related Institution

Shanghai Aerospace Electronic Technology Institute

State Key Laboratory of Advanced Optical Communication Systems and Networks, Shanghai Jiao Tong University

Troop No.PLA

State Key Laboratory of Quantum Optics and Quantum Optics Devices, Shanxi University

College of Physics and Optoelectronics, Taiyuan University of Technology

Postal code：430205
Technical support is provided by Beijing Founder electronics co., LTD 鄂ICP备2022010197 鄂公网安备 42011202002092号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.
Total Visits：75842 Visits Today：30

⁰