Design of ASIC chips for 60 Gbit/s broadband circuit switching

Meng Lilin

doi:10.13756/j.gtxyj.2007.04.014

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Design of ASIC chips for 60 Gbit/s broadband circuit switching

- Design of ASIC chips for 60 Gbit/s broadband circuit switching
- Study on Optical communication Issue 4, Pages: 49-51(2007)
- 作者机构：
  
  西安邮电学院ASIC设计中心,陕西,西安,710061
- 作者简介：
- 基金信息：
- DOI：10.13756/j.gtxyj.2007.04.014
  CLC： TN492
- Published：2007，
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[1]孟李林.60Gbit/s宽带电路交换ASIC芯片设计[J].光通信研究,2007(04):49-51.

Meng Lilin. Design of ASIC chips for 60 Gbit/s broadband circuit switching. [J]. (4):49-51(2007)
[1]孟李林.60Gbit/s宽带电路交换ASIC芯片设计[J].光通信研究,2007(04):49-51. DOI： 10.13756/j.gtxyj.2007.04.014.

Meng Lilin. Design of ASIC chips for 60 Gbit/s broadband circuit switching. [J]. (4):49-51(2007) DOI： 10.13756/j.gtxyj.2007.04.014.

摘要

文章提出了一种60 Gbit/s宽带电路交换专用集成电路（ASIC）芯片的设计实现方案。针对设计芯片速度快、规模大和功耗大等特点

给出了采用流水线设计思想和优化结构处理技术的电路设计解决方案。同时还给出了采用现场可编程门阵列（FPGA）芯片对设计电路进行功能验证的结果和ASIC流片的基本数据。

Abstract

This article presents a design scheme for ASIC chips used for 60 Gbit/s broadband circuit switching.A pipeline design concept and optimum structuring technology are put forward for fast-speed

large-size and high-power-consumption chips.The circuit functions are verified with altera FPGA chips and the results of the verification and its ASIC synthesis with Synopsys DC are given.

关键词

专用集成电路现场可编程门阵列同步数字体系电路交换

Keywords

ASICFPGASDHcircuit switch

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Related Institution

1,2), ZHANG Qian-lin~1, Lü Jian-dong~2ghai

Xi’an Institute of Posts and Telecommunications

陕西西安710061

上海200433

Shanghai Aerospace Electronic Technology Institute

Postal code：430205
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