Study on a novel FPGA hardware implementation method for AES algorithms

Li Xia; Huang Yuanbo

doi:10.13756/j.gtxyj.2008.04.002

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Study on a novel FPGA hardware implementation method for AES algorithms

- Study on a novel FPGA hardware implementation method for AES algorithms
- Study on Optical communication Issue 4, Pages: 23-24(2008)
- 作者机构：
  
  光纤通信技术和网络国家重点实验室武汉邮电科学研究院
- 作者简介：
- 基金信息：
- DOI：10.13756/j.gtxyj.2008.04.002
  CLC： TN791
- Published：2008，
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[1]李霞,黄元波.一种新的AES算法的FPGA实现方法研究[J].光通信研究,2008(04):23-24+47.

Li Xia, Huang Yuanbo. Study on a novel FPGA hardware implementation method for AES algorithms. [J]. (4):23-24(2008)
[1]李霞,黄元波.一种新的AES算法的FPGA实现方法研究[J].光通信研究,2008(04):23-24+47. DOI： 10.13756/j.gtxyj.2008.04.002.

Li Xia, Huang Yuanbo. Study on a novel FPGA hardware implementation method for AES algorithms. [J]. (4):23-24(2008) DOI： 10.13756/j.gtxyj.2008.04.002.

摘要

文章主要讨论了高级加密标准（AES）算法在主频较低情况下的硬件实现。根据AES算法的结构特点和硬件实现的具体原理

提出了一种AES算法的硬件实现方法。该方法采用在单个时钟周期内执行多轮加密的策略

并使用流水线

做到了兼顾加密的速度和较低的时钟频率。最后

与现有的方法进行了分析比较。

Abstract

This paper focuses on the hardware implementation of AES algorithms at low master frequency.On the basis of the characteristics of AES algorithms and the specific principle of hardware implementation

it brings forward a hardware implementation method for AES algorithms

by which considerations are given to both encryption speed and low clock frequency by using the strategy of implementing multiple encryptions in single clock period and the pipeline.Finally

it makes analysis of and comparison between this new method and the existing ones.

关键词

密钥扩展轮变换流水线

Keywords

key expansionround transformationpipeline

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State Key Laboratory of Optical Communication Technologies and Networks

Wuhan FiberHome Network Co.,Ltd.

ASIC Center of Xi’an Institute of Post and Telecommunications

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