An OTDR scheme based on FPGA and ARM architecture

Zhu Xiaolong; Ruan Zhiguang; Guo Feng; Wen Changqing

doi:10.13756/j.gtxyj.2012.03.009

您当前的位置：

首页 >

文章列表页 >

An OTDR scheme based on FPGA and ARM architecture

- An OTDR scheme based on FPGA and ARM architecture
- Study on Optical communication Issue 3, Pages: 33-35(2012)
- 作者机构：
  
  上海光维通信技术股份有限公司
- 作者简介：
- 基金信息：
- DOI：10.13756/j.gtxyj.2012.03.009
  CLC： TN791;TP368.1
- Published：2012，
扫描看全文
[1]朱小龙,阮志光,郭峰,温长青.基于FPGA和ARM架构的OTDR方案[J].光通信研究,2012(03):33-35.

Zhu Xiaolong, Ruan Zhiguang, Guo Feng, et al. An OTDR scheme based on FPGA and ARM architecture. [J]. (3):33-35(2012)
[1]朱小龙,阮志光,郭峰,温长青.基于FPGA和ARM架构的OTDR方案[J].光通信研究,2012(03):33-35. DOI： 10.13756/j.gtxyj.2012.03.009.

Zhu Xiaolong, Ruan Zhiguang, Guo Feng, et al. An OTDR scheme based on FPGA and ARM architecture. [J]. (3):33-35(2012) DOI： 10.13756/j.gtxyj.2012.03.009.

摘要

为开发实用便携的嵌入式OTDR（光时域反射仪）

文章提出了一种采用FPGA（现场可编程门阵列）进行数据采集和累加平均等简单处理、ARM（精简指令集处理器）进行人机交互和数据分析的设计方案。介绍了该系统的工作原理、硬件设计和软件设计

并对其中FPGA程序进行了重点阐述。实验结果表明

此设计方案融合了两种芯片的特性和优势

系统性能获得了较大提升。

Abstract

To develop a practical portable embedded OTDR

this paper presents and implements a design scheme

in which Field Programmable Gates Array（FPGA） is adopted for data acquisition

accumulation and averaging and ARM for human-computer interaction and data analysis.It briefly introduces the system working principle and hardware and software design

with emphasis on the FPGA procedures.The experimental results show that this design converges the characteristics and advantages of above two chips and enormously improves the system performance.

关键词

光时域反射仪现场可编程门阵列精简指令集处理器

Keywords

OTDRFPGAARM

references

更多指标>

Views

129

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

The 2.5 Gbit/s Optical System Used in Illumination Guidance System based on Serial Parallel Transceiver

Automatic Gain Control Method and Implementation of Distributed Raman Fiber Amplifier

A Scheme for Long-distance High-resolution Detection of Fiber Link

Real-time Implementation of Chaos Synchronization Using Neural Network based on FPGA

Real-Time and Parallel Post-Processing for High-Speed Quantum Random Number Generation

Related Author

No data

Related Institution

Shanghai Aerospace Electronic Technology Institute

Accelink Technologies Co., Ltd.

Wuhan Research Institute of Posts and Telecommunications

Pilot National Laboratory for Marine Science and Technology

College of Ocean Science and Engineering, Shandong University of Science and Technology

⁰