Design and implementation of demapping circuits from OTU2 to ODU2 in OTN

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- Design and implementation of demapping circuits from OTU2 to ODU2 in OTN
- Study on Optical communication Issue 3, Pages: 15-17(2014)
- 作者机构：
  
  西安邮电大学电子工程学院
- 作者简介：
- 基金信息：
- DOI：10.13756/j.gtxyj.2014.03.005
  CLC： TN929.11
- Published：2014，
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[1]邵瑞瑞,孟李林,李小龙,钟李全.OTN中OTU2到ODU2解映射电路设计与实现[J].光通信研究,2014(03):15-17+20.

Shao Ruirui, Meng Lilin, Li Xiaolong, et al. Design and implementation of demapping circuits from OTU2 to ODU2 in OTN. [J]. (3):15-17(2014)
[1]邵瑞瑞,孟李林,李小龙,钟李全.OTN中OTU2到ODU2解映射电路设计与实现[J].光通信研究,2014(03):15-17+20. DOI： 10.13756/j.gtxyj.2014.03.005.

Shao Ruirui, Meng Lilin, Li Xiaolong, et al. Design and implementation of demapping circuits from OTU2 to ODU2 in OTN. [J]. (3):15-17(2014) DOI： 10.13756/j.gtxyj.2014.03.005.

为了在解映射过程中尽量减少锁相环的使用

设计了一种基于同步时钟产生的均匀缺口时钟来实现解帧、去FEC（前向纠错）以及OTU2（光传输单元）解映射到ODU2（光数据单元）的同步电路。通过仿真和FPGA（现场可编程门阵列）验证了该电路功能的正确性。结果表明

该电路能够实时、准确地完成OTU2到ODU2的解映射。

In order to reduce the use of PLL as much as possible in the process of demapping

this paper designs a sync circuit. On the basis of the uniform gaps in the clock produced by a sync clock

the sync circuit is used to realize deframing

de-FEC and demapping from OTU2to ODU2.Simulation and FPGA test results verify the correctness of the circuit functions

indicating that this circuit can accomplish demapping from OTU2to ODU2in real-time and accurately.

缺口时钟成帧器异步映射

gap in the clockdeframerasynchronous mapping

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Design and implementation of mapping circuit from ODU₀ to ODU₁ in OTN

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School of Computer,Xi’an University of Posts and Telecommunications

School of Postgraduates,Xi’an University of Posts and Telecommunications

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