Design of Single-Chip Optical Network Unit based on High Speed Serial Transceiver

CHEN Xiao-yi; GAO Ming-yi; YE Yang; SHAO Wei-dong

doi:10.13756/j.gtxyj.2019.02.003

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Design of Single-Chip Optical Network Unit based on High Speed Serial Transceiver

- Design of Single-Chip Optical Network Unit based on High Speed Serial Transceiver
- Study on Optical communication Issue 2, Pages: 11-14(2019)
- 作者机构：
  
  苏州大学电子信息学院
- 作者简介：
- 基金信息：
- DOI：10.13756/j.gtxyj.2019.02.003
  CLC： TN929.1
- Published：2019，
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[1]陈潇逸,高明义,叶阳,邵卫东.基于高速串行收发器的单芯片光网络单元设计[J].光通信研究,2019(02):11-14.

CHEN Xiao-yi, GAO Ming-yi, YE Yang, et al. Design of Single-Chip Optical Network Unit based on High Speed Serial Transceiver. [J]. (2):11-14(2019)
[1]陈潇逸,高明义,叶阳,邵卫东.基于高速串行收发器的单芯片光网络单元设计[J].光通信研究,2019(02):11-14. DOI： 10.13756/j.gtxyj.2019.02.003.

CHEN Xiao-yi, GAO Ming-yi, YE Yang, et al. Design of Single-Chip Optical Network Unit based on High Speed Serial Transceiver. [J]. (2):11-14(2019) DOI： 10.13756/j.gtxyj.2019.02.003.

摘要

针对工业应用无源光网络开发周期长

灵活性差的缺陷

提出利用现场可编程门阵列内部集成的高速串行收发器代替外接物理层芯片的设计方案。改进分层设计模型和数据帧结构

突发同步字符长度可根据光线路终端收发器突发同步性能在线重配置。板级验证结果表明

系统能够在3.125 Gbit/s速率下完成数据帧接收和突发模式发送

具有兼容性高、复杂度低等诸多优势。

Abstract

To solve the issues of the long development cycle and poor flexibility of industrial Passive Optical Metwork（PON）

we proposed a scheme composed of Field Programmable Gate Array（FPGA） with integrated high-speed serial transceivers instead of external physical layer chip. The hierarchical design model and data frame structure are improved and the character length of burst synchronization can be reconfigured online according to the burst synchronization performance of the optical line terminal transceiver. The results of board level verification show that the system can complete the data frame reception and burst mode transmission at the rate of 3.125 Gbit/s

with advantages of high compatibility and low complexity.

关键词

无源光网络光网络单元串行收发器突发数据帧现场可编程门阵列

Keywords

PONoptical network unitserial transceiverburst data frameFPGA

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