SHI Hong-hao, Lü Jian-xin. An Implementation of Low Latency FEC Encoding and Decoding for 100 Gbit/s/400 Gbit/s Optical Network based on FPGA. [J]. (6):21-26(2019)
SHI Hong-hao, Lü Jian-xin. An Implementation of Low Latency FEC Encoding and Decoding for 100 Gbit/s/400 Gbit/s Optical Network based on FPGA. [J]. (6):21-26(2019) DOI: 10.13756/j.gtxyj.2019.06.005.
An Implementation of Low Latency FEC Encoding and Decoding for 100 Gbit/s/400 Gbit/s Optical Network based on FPGA
Problems of bit error rate rising due to Optical Signal-to-Noise Ratio(OSNR) worsening in beyond-100 Gbit/s optical network can be overcomed by utilizing feed Forward Error Correction(FEC) codes which are comprehensively applied in optical networks. Traditional encoders with high latency cannot meet the requirements of high-speed optical network
and studies on high-speed encoder are seldom. Studies on decoders usually focus on key equation solving algorithms rather than low latency decoding schemes. A parallel encoding and decoding scheme is proposed in this paper for KP4 FEC
i.e. RS(544
514) code
with the encoder’s throughput reaching above 17 Gbit/s
and latency lower than 0.3 μs
while the decoder’s throughput reaching above 66 Gbit/s