【Objective】

2

For the implementation of Trans Impedance Amplifier (TIA) in 400 Gbit/s Dual Polarization (DP)– 16 Quadrature Amplitude Modulation (QAM) coherent receiver.

【Methods】

2

A 64 GBaud dual channels differential linear TIA in advanced Silicon Germanium Bipolar Complementary Metal Oxide Semiconductor Heterojunction Bipolar Transistor (SiGe BiCMOS HBT) process is proposed. The chip consists of two identical signal amplifying paths for the I and Q signals of Coherent Receiver. The path utilities full differential shunt-shunt feedback structure as TIA stage

and consequent two Variable Gain Amplifier (VGA) stages in series to amplify further

and Current Mode Logic (CML) buffer with single-end 50 Ω output impedance as the output stage. The chip integrates two independent Direct Current Restore (DCR) loops to remove the input direct current component and direct current offset at the core output node

and integrates Direct Current Offset Cancellation (DCOC) loop to remove the output direct current offsets due to the differential pairs mismatch along the VGA and buffer stages. An Automatic Gain Control (AGC) loop is built in to adjust automatically the trans-impedance gain of TIA stage and gain of VGA stages based on input amplitude detecting

which is aimed to avoid saturation distortion. To optimize output impedance matching and reduce the impact of parasitic capacitance of Electrical Static Discharge (ESD) diodes

a three ports bridge-T network inductive peaking technique is inserted in the output node to optimize the output return loss and improve the bandwidth. The chip is designed and manufactured in advanced SiGe BiCMOS HBT process. The die size is 1.6 mm×1.8 mm

and the channel pitch is 625 μm. The chip is assembled with Photodiode (PD)

junction capacitance

C

pd

=50 fF and other coherent optical components into Integrated Coherent Receiver (ICR) for testing.

【Results】

2

The test results show that

the differential gain is 5 kΩ

and the 3 dB bandwidth is 32 GHz. The Total Harmonic Distortion (THD) is less than 2%

and the overload optical input is 3 dBm. The chip is powered by a single 3.3 V supply

and the static power dissipation is only 250 mW.

【Conclusion】

2

The chip can be applied in 64 GBaud coherent receiver

and implement 400 Gbit/s per lambda transmission with DP-16QAM modulation.