This paper presents two circuit techniques of full switching delay cells and dual-delay path to design a high operate frequency
low noise ring oscillator. An even-stage ring oscillator is adopted to generated two quadrature output clock of 90 degrees phase differences. The chip is fabricated in 0.18 μm CMOS process
VCO operates at 4.9 GHz to 5.5 GHz
the simulated phase noise is -119.3 dBc/Hz at 5 MHz offset. With the 1.8 V-power supply