In the design of EOS

the MAC frames received by Ethernet are stored firstly and then removed by eneapsulation engine. This paper describes the realization process in which the SDRAM is used as and off-chip memory.Utilizing the features of SDRAM

especially its advantages of high-speed and large capacity

the buffer area on ASIC chip can be certainly reduced and the Ethernet data can be accurately mapped into the SDH transport network. The design has been verified on FPGA and passed the IP network analyzer test.