This article presented the design of a monolithic optical receiver circuit for SDH STM-16 （2.5 Gbit/s） fiber-optic communications. The IC was implemented in TSMC 0.25 μm CMOS process. The 1.25 GHz clock can be recovered in response to 5 μA 2.5 Gbit/s PRBS input data (2

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and the 2.5 Gbit/s PRBS data can be demultiplexed to four 625 Mbit/s data. The output clock and data are the 400 mV standard PCML voltage level. The 1.04 mm×0.97 mm IC consumes 850 mW under a single 3.3 V power supply.