Sharp increase of network data amount causes rapid bandwidth consumption and network congestion

which places still higher requirements on Packet Transport Network（PTN）chips in terms of forwarding capacity

clock rate

congestion avoidance and flow management.In order to improve the clock rate and reduce the circuit design complexity of the IP multicast lookup circuits in these network chips

this paper completes this circuit design by adopting pipeline architecture and looking up the intermediate state information using the RAM record.It conducts hardware verification on Altera series FPGA development board EP4SGX230KF40C2ES and the results show that this circuit can complete the IP multicast lookup function and works steadily at 200MHz.