In order to absorb the frequency offset generated due to source and destination clocks from different sources in Optical Transport Networks（OTN）

a circuit is designed by asynchronous mapping

in which sync clock-based ODU0 that generates uniform clock gaps is mapped to ODU1 and the clock gaps are generated in the mapping by asynchronous FIFO.The client data is processed by this clock and mapped into appropriate time slots.Simulation and FPGA test results indicate that this circuit can complete the traditional mapping from ODU0 to ODU1 in real-time and accurately.Compared with the traditional circuits

it greatly decreases the usage of PLL and makes the circuit more economical.