This paper designs an I2C bus limit test controller for assessing the robustness of the I2C bus communication of optical transceiver modules.In this design

the parameters exceed the limits by a certain range according to the I2C communication protocol.This controller is designed on CPLD using Verilog HDL

which is used to perform two main functions

I2C frequency test and bus line characteristics test.Software simulation and hardware implementation verify the correctness of this design.This controller can also conduct tests of other kinds of I2C slave devices with the only need to change device address

offset address and other relevant parameters.