一种64 GBaud双通道差分线性跨阻放大器

林少衡

doi:10.13756/j.gtxyj.2023.06.007

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一种64 GBaud双通道差分线性跨阻放大器

光电器件研究与应用 | 更新时间：2023-12-07

- 一种64 GBaud双通道差分线性跨阻放大器
- A 64 GBaud Dual Channel Differential Linear Trans-impedance Amplifier
- 光通信研究 2023年第6期页码：57-63
- 作者机构：
  
  厦门优迅高速芯片有限公司，福建　厦门　361012
- 作者简介：
  
  林少衡，高级工程师。E-mail：linsh@uxfastic.com
- 基金信息：
- DOI：10.13756/j.gtxyj.2023.06.007
  中图分类号： TN432
- 纸质出版日期：2023-12-10，
  
  收稿日期：2023-05-26，
  
  修回日期：2023-06-16，
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林少衡.一种64 GBaud双通道差分线性跨阻放大器[J].光通信研究，2023(6):57-63.

Lin S H. A 64 GBaud Dual Channel Differential Linear Trans-impedance Amplifier[J]. Study on Optical Communications, 2023(6):57-63.
林少衡.一种64 GBaud双通道差分线性跨阻放大器[J].光通信研究，2023(6):57-63. DOI： 10.13756/j.gtxyj.2023.06.007.

Lin S H. A 64 GBaud Dual Channel Differential Linear Trans-impedance Amplifier[J]. Study on Optical Communications, 2023(6):57-63. DOI： 10.13756/j.gtxyj.2023.06.007.

摘要

【目的】

针对400 Gbit/s双偏振（DP）-16正交幅度调制（QAM）相干光接收机应用的核心线性跨阻放大器（TIA）实现问题。

【方法】

文章基于先进锗硅异质结双极型互补氧化物半导体（SiGe BiCMOS HBT）工艺实现了一种64 GBaud双通道差分线性TIA。芯片核心由两路完全相同的信号放大通道组成，以输入放大相干接收的I和Q分量。信号放大通道电路采用全差分电压并联负反馈结构作为核心TIA，采用两级差分可变增益放大器（VGA）级联结构实现进一步信号放大，单端输出阻抗50 Ω的电流模逻辑（CML）缓冲器作为输出级。在输入两端，分别引入了独立的直流恢复（DCR）环路以消除输入信号直流分量及差分输出直流失调，并引入了全差分直流失调消除（DCOC）以消除工艺失配产生的输出直流失调，提高电路线性度。为了提高输入动态线性范围，引入了自动增益控制（AGC）电路以自动根据输入信号强度调节TIA跨阻及VGA增益，避免信号饱和失真；为了优化输出阻抗匹配，减小静电放电（ESD）二极管寄生电容影响，输出级采用了三端口桥式－T网络（T-Coil）电感峰化负载结构，以改善输出回损，提高带宽。芯片采用先进SiGe BiCMOS HBT工艺设计制造，裸片尺寸为1.6 mm×1.8 mm，通道间距为625 μm。芯片搭配结电容

=50 fF的光电二极管（PD）及相干接收光路元器件封装成集成相干接收机（ICR）组件进行测试。

【结果】

封测结果表明，该芯片小信号跨阻增益为差分5 kΩ，3 dB带宽为32 GHz，总谐波（THD）小于2%，饱和输入功率达到3 dBm，整个芯片由3.3 V单电源供电，静态功耗仅为250 mW。

【结论】

芯片可用于64 GBaud的相干接收应用，配合DP-16QAM调制，可实现单波400 Gbit/s传输应用。

Abstract

【Objective】

For the implementation of Trans Impedance Amplifier (TIA) in 400 Gbit/s Dual Polarization (DP)– 16 Quadrature Amplitude Modulation (QAM) coherent receiver.

【Methods】

A 64 GBaud dual channels differential linear TIA in advanced Silicon Germanium Bipolar Complementary Metal Oxide Semiconductor Heterojunction Bipolar Transistor (SiGe BiCMOS HBT) process is proposed. The chip consists of two identical signal amplifying paths for the I and Q signals of Coherent Receiver. The path utilities full differential shunt-shunt feedback structure as TIA stage

and consequent two Variable Gain Amplifier (VGA) stages in series to amplify further

and Current Mode Logic (CML) buffer with single-end 50 Ω output impedance as the output stage. The chip integrates two independent Direct Current Restore (DCR) loops to remove the input direct current component and direct current offset at the core output node

and integrates Direct Current Offset Cancellation (DCOC) loop to remove the output direct current offsets due to the differential pairs mismatch along the VGA and buffer stages. An Automatic Gain Control (AGC) loop is built in to adjust automatically the trans-impedance gain of TIA stage and gain of VGA stages based on input amplitude detecting

which is aimed to avoid saturation distortion. To optimize output impedance matching and reduce the impact of parasitic capacitance of Electrical Static Discharge (ESD) diodes

a three ports bridge-T network inductive peaking technique is inserted in the output node to optimize the output return loss and improve the bandwidth. The chip is designed and manufactured in advanced SiGe BiCMOS HBT process. The die size is 1.6 mm×1.8 mm

and the channel pitch is 625 μm. The chip is assembled with Photodiode (PD)

junction capacitance

=50 fF and other coherent optical components into Integrated Coherent Receiver (ICR) for testing.

【Results】

The test results show that

the differential gain is 5 kΩ

and the 3 dB bandwidth is 32 GHz. The Total Harmonic Distortion (THD) is less than 2%

and the overload optical input is 3 dBm. The chip is powered by a single 3.3 V supply

and the static power dissipation is only 250 mW.

【Conclusion】

The chip can be applied in 64 GBaud coherent receiver

and implement 400 Gbit/s per lambda transmission with DP-16QAM modulation.

关键词

64 GBaud差分线性跨阻放大器可变增益放大器三端口桥式－T网络锗硅异质结双极型互补氧化物半导体

Keywords

64 GBauddifferential linear TIAVGAT-CoilSiGe BiCMOS HBT

references

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