用于PON的低成本CMOS BM-TIA设计

赵婉青; 夏翼飞; 李佳; 徐颂秦; 马帅哲; 杨睿煊; 耿莉; 李丹

doi:10.13756/j.gtxyj.2025.230163

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用于PON的低成本CMOS BM-TIA设计

光电器件研究与应用 | 更新时间：2025-02-17

- 用于PON的低成本CMOS BM-TIA设计
- Low-cost CMOS BM-TIA Design for PON
- 光通信研究 2025年第1期
- 作者机构：
  
  西安交通大学　电子与信息工程学部微电子学院，西安　 710049
- 作者简介：
  
  赵婉青（1999－），女，陕西咸阳人。硕士，主要研究方向为高速宽带模拟电路。
  李丹，副教授。E-mail：dan.li@xjtu.edu.cn
- 基金信息：
  
  国家重点研发计划资助项目(2022YFB2803301);国家自然科学基金面上资助项目(62074126)
- DOI：10.13756/j.gtxyj.2025.230163
  中图分类号： TN722
- 纸质出版日期：2025-02-10，
  
  收稿日期：2023-10-31，
  
  修回日期：2023-12-04，
- 稿件说明：
移动端阅览
赵婉青，夏翼飞，李佳，等. 用于PON的低成本CMOS BM-TIA设计[J]. 光通信研究，2025(1): 230163.

Zhao W Q, Xia Y F, Li J, et al. Low-cost CMOS BM-TIA Design for PON[J]. Study on Optical Communications, 2025(1): 230163.
赵婉青，夏翼飞，李佳，等. 用于PON的低成本CMOS BM-TIA设计[J]. 光通信研究，2025(1): 230163. DOI： 10.13756/j.gtxyj.2025.230163.

Zhao W Q, Xia Y F, Li J, et al. Low-cost CMOS BM-TIA Design for PON[J]. Study on Optical Communications, 2025(1): 230163. DOI： 10.13756/j.gtxyj.2025.230163.

摘要

【目的】

在高速率无源光网络（PON）需求的快速增长下，低成本低噪声突发模式跨阻放大器（BM-TIA）成为其关键的制约因素。文章基于低成本40 nm互补金属氧化物半导体（CMOS）工艺，设计了一种适用于10吉比特对称无源光网络（XGS-PON）的快速建立低噪声BM-TIA，其可兼容12.5、10.0和2.5 Gbit/s 3种信号速率。

【方法】

为突破CMOS工艺的带宽和噪声瓶颈，TIA通过多级放大、输入电感均衡网络及提高电源电压的方法实现了要求的低噪声。采用前向放大器与反馈电阻共同调节的增益调节方式，实现了3档位的增益变化和速率变化。针对突发模式信号采用快速直流（DC）消除环路（AOC）来精准消除雪崩击穿二极管（APD）输入的DC电流，运用电荷分享技术加速失调消除环路的建立，并通过转换AOC环路时间常数的方法来抑制基线漂移。

【结果】

芯片采用40 nm CMOS工艺设计制造，裸片尺寸为945 μm×945 μm。芯片搭配商用10 Gbit/s APD进行同轴罐（TO-CAN）封装测试。测试结果表明，在12.5、10.0以及2.5 Gbit/s速率下，芯片的灵敏度分别为－29.7，－33.0和－37.6 dBm。在不同速率下，饱和输入光电流均可达2.5 mA，实现了24.7、28.2和32.8 dB的大输入动态范围。芯片的静态功耗为82.5 mW，在整个输入光功率范围内，突发模式下AOC的建立时间均小于23 ns。

【结论】

将文章所提芯片应用于XGS-PON，不但为基于CMOS工艺的低成本低噪声BM-TIA设计提供了借鉴，也对更高速率PON场景下的芯片设计具有指导意义。

Abstract

【Objective】

With the rapid growth in demand for high-speed Passive Optical Networks (PONs)

low-cost

low-noise Burst Mode Transimpedance Amplifiers (BM-TIAs) have become a key limiting factor. In this paper

a fast-settling

low-noise BM-TIA for 10 Gigabit Symmetrical Passive Optical Network (XGS-PON) is designed based on a low-cost 40 nm Complementary Metal Oxide Semiconductor (CMOS) process

which is compatible with three signal rates: 12.5

10.0 and 2.5 Gbit/s.

【Methods】

To overcome the bandwidth and noise limitations of the CMOS process

the TIA achieves the required low noise through multi-stage amplification

an input inductor balancing network

and an increased power supply voltage. The gain adjustment is achieved by a combination of feedforward amplification and feedback resistance

enabling three gain levels and rate variations. To address burst-mode signals

fast direct current cancellation loop Automatic Offset Cancellation (AOC) is used to accurately eliminate the Direct Current (DC) input from the Avalanche Photodiode (APD). The charge-sharing techniques are employed to speed up the establishment of the offset cancellation loop and suppress the baseline drift by converting the AOC loop time constant.

【Results】

The chip is designed and manufactured using a 40 nm CMOS process

with a die size of 945 μm×945 μm. The chip is tested with a commercial 10 Gbit/s APD in a Transistor Outline Can (TO-CAN) package. The test results show that the sensitivity of the chip at 12.5

10.0 and 2.5 Gbit/s is －29.7，－33.0 and －37.6 dBm

respectively. The saturated input photocurrent can reach 2.5 mA at different data rates

and the chip achieves a large input dynamic range of 24.7

28.2 and 32.8 dB for the three data rates. The static power consumption of the chip is 82.5 mW

and the AOC settling time in burst-mode is less than 23 ns across the entire input optical power range.

【Conclusion】

This chip

applied in XGS-PON

not only provides reference for the design of low-cost and low-noise BM-TIAs based on CMOS process but also has guiding significance for chip design in higher-speed PON scenarios.

关键词

Keywords

references

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